1. Field of the Invention
The present invention relates to a semiconductor device comprising an MIM (Metal-Insulator-Metal) capacitor which is a capacitance element having such a metal-insulator-metal structure that a dielectric film is provided between two metallic layers and a method of manufacturing the semiconductor device.
2. Description of the Related Art
It is pursued in recent years to provide an analog device and a CMOS logic device on one chip, and the CMOS logic device is increasingly miniaturized from year to year. In the case where the gate length of a MOS transistor is at most approximately 0.1 μm, it is demanded that the wiring resistance be further reduced. Therefore, Cu (copper), which is a low-resistance material, is used as a material for a metallic wiring, and the damocene process has been made commercially available as a method of forming the metallic wiring.
The one-chip configuration of an analog device and a CMOS logic device and the application of Cu wiringhave generated various problems in the structure of an MIM capacitor provided in the analog device. Further, an electrode of the MIM capacitor formed by means of the damocene process also undergoes a problem resulting from the damocene process. Describing the problem, the flatness of a lower electrode in the MIM capacitor deteriorates due to dishing and erosion.
In the MIM capacitor of an analog device in which the Cu wiring formed by the damocene process constitute the electrode, the method wherein the electrode is formed in a comb shape was proposed in order to solve, particularly, the dishing problem generated in the electrode in the damocene process as recited in the conventional example 1 (No. 2001-237375 of the Japanese Patent Applications Laid-Open).
In the conventional damocene process, the density of the metallic wirings is increased in a larger area in order to reduce a parasitic resistance of the electrode generated when the lower electrode is formed, which, however, generates erosion. As a result, such a trouble as the variation of a capacitance value of the MIM capacitor occurs.
Below is described the erosion in the CMP (Chemical Mechanical Polishing). In the case where a structure, wherein Cu is provided in an upper layer and Cu and an interface between Cu and a conducive film is provided in a lower layer, is polished by means of the CMP, when Cu is continuously polished and the polishing process has reached a surface of the lower layer (Cu, interface between Cu and conductive film), the polish of the conductive film is substantially halted though the polish of Cu still advances (because a polishing rate of Cu is higher than that of the conductive film). The different polishing rates may cause such a state generated in the polishing process; however, a coverage shape of the plated Cu film has been suggested as a main cause thereof, for which FIG. 12 illustrating the conventional example 1 described earlier can be referred to.
As the polish of Cu selectively advances, Cu constituting the Cu wiring consequently grows concave, which generates a defference in level between the Cu wiring and the conductive film. Once the defference in level is generated, the conductive film adjacent to the concave Cu wiring is locally subjected to a high pressure. As a result, the polish of that part of the conductive film is restarted by a mechanical action thereby generated, and an insulation film therebelow may also be polished. On the other hand, the polish of the Cu wiring is not interrupted but continued by a chemical action. When these different polishing processes are repeatedly performed, the Cu wirings which are densely provided consequently have a concave portion. This phenomenon is called erosion.
The higher the metallic wiring density is, the more the erosion advances, because a larger number of Cu wirings grow concave as the metallic wirings are more densely provided. As a result, a high pressure is applied to the conductive film which is less densely provided in the same region, and the concave portion thereby further advances.
The conventional example 2 (J. M. Steigerwald, et al. “Pattern Geometry Effects in the Chemical-Mechanical Polishing of Inlaid Copper Structures,” J. Electrochem. Soc., 141: 10, 2842-2848, October, 1994) recites a relationship between an erosion amount [nm] and a pattern density [%], which is illustrated in FIG. 20. According to FIG. 20, in the case where the metallic wirings are provided in such a large area as, for example, 200 μm square, it is necessary to set the metallic wirings as follows in order to reduce a desired parasitic resistance to at most 100 mΩ.
metallic wiring resistance width:2 μmmetallic wiring density:at least 80%
However, as illustrated in FIG. 20, the erosion amount reaches a value exceeding 280 nm in the case where the metallic wiring resistance width is 5 μm and the metallic wiring density is 80% reaches a little above 280 nm. Therefore, the wiring film thickness of 30 nm would be necessary in the case of an MIM capacitance film wherein a silicon nitride film is used as the conductive film and the desired capacitance value (for example, 2 fF/mm2) can be obtained. However, when the wiring film thickness of 30 nm is secured in the state where the erosion exceeding 280 nm is generated, the generated difference in level will be at least nine times as deep in such a wiring structure. In a similar manner, the wiring film thickness of 50 nm would be necessary in the case of an MIM capacitance film wherein a tantalum oxide film is used as the conductive film and a desired capacitance value (for example, 2 fF/mm2) can be obtained. However, when the wiring film thickness of 50 nm is secured in the state where the erosion exceeding 280 nm is generated, the generated difference in level will be at least five times as deep in such a wiring structure. To the variation of the capacitance value are added 10% variation of the capacitance film thickness and approximately 5% increase in an effective surface area which constitutes the capacitance.
As is learnt from the foregoing description, the erosion amount is significantly increased in the case the metallic wiring density is increased in a larger area, according to the conventional methods, which makes it quite difficult to realize a desired capacitance variation (for example, approximately 10%). Further, it is clear from FIG. 21 (illustrating a relationship between the dishing amount [nm] and the pattern density [%] in each metallic wiring width in the conventional example 2) that the purpose of setting the metallic wiring width to 2 μm is to significantly lessen the concave portion generated in the metallic wiring. The metallic wiring of 2 μm denotes such a metallic wiring width that can limit the film thickness to at most 30 nm in the silicon nitride film and to at most 50 nm in the tantalum oxide film in the case where the dishing amount is approximately 20 nm. When all of the large area of 200 μm square is directly used for the Cu wirings, the dishing amount results in 520 μm, in which case the difference in level is maximized. Therefore, the Cu wirings having such a large area as 200 μm square cannot be used as the electrode of the MIM capacitance.